1. Field of the Invention
The present invention relates to memory devices and, in particular, to a virtual ground flash electrically erasable programmable read only memory (EEPROM) array that is based on a source-coupling, split-gate cell.
2. Discussion of the Prior Art
In order to realize flash EEPROM memory arrays having a density of 4M bits or higher, technology innovation in both memory cell structure and array architecture is required.
In the past, Intel's well-know "T-shaped" ETOX cell has been intensively utilized in flash memory applications because of its small size and simple stacked gate structure.
FIG. 1 shows a portion of an ETOX cell array in which two ETOX cells, e.g. cells 12a and 12b, share one drain contact 13. FIG. 2 shows a cross-section of an individual ETOX cell taken along line A--A in FIG. 1 (i.e., along polysilicon (poly2) word line 16). FIG. 3 shows a cross-section of an ETOX cell taken along line B--B in FIG. 1 (i.e., along bit line 18).
The ETOX cell 12 is implemented utilizing a very thin gate oxide 20 (about 100 .ANG. thick) and a graded n+/n- source region 22 to enhance reliability by reducing the field across the source junction when the cell 12 is being erased.
As shown in FIG. 4A, the ETOX cell 12 is written in a conventional manner. That is, hot electrons are injected from the drain junction 14 into the polysilicon (poly1) floating gate 24 when the polysilicon (poly2) word line (control gate) 16 is biased at a programming voltage Vpp, the n+ drain bit line 14 is at the positive supply voltage Vcc and the graded source region 22 is held at ground (Vss).
As shown in FIG. 4B, erasing the ETOX cell 12 is performed by Fowler-Nordheim tunnelling of electrons from the floating gate 24 through the thin oxide 20 to the graded source region 22 when the source region 22 is at the programming voltage Vpp, the drain 14 is floating and the word line 16 is at ground (Vss). As stated above, the source 22 is graded to prevent junction breakdown during the erase operation.
Both Kodama et al., "A 5 V Only 16M bit Flash EEPROM Cell Using Highly Reliable Write/Erase Technologies", Symp on VLSI Technology, P. 75, 1990", and Ajika et al., "A 5 Volt Only 16M Bit Flash EEPROM Cell with a Simple Stacked Gate Structure", IEDM, p. 115, 1990, have reported 16M bit flash EEPROM arrays utilizing the ETOX cell. However, the conventional operational problems associated with the ETOX array, such as write disturb, over-erase and soft write, are minimized in these architectures only by utilizing tight process and bias controls and by utilizing critical operational sequences such as intelligent erase and pre-write before erase.
The term "write disturb" refers to disturbances caused to neighboring cells as a result of the high voltages applied to the gate and drain of a selected cell during a write operation. Write disturb includes "gate disturb", "drain disturb" and "unintentional write".
Gate disturb: for cells along the selected word line, the gate-to-source bias is the gate voltage Vpp, which can cause electrons to tunnel from the source to the floating gate, thus shifting the cell's threshold voltage upward.
Drain disturb: for cells along the unselected word line and the selected bit line, the drain-to-gate bias is the drain voltage, which can cause electrons to tunnel from the floating gate to the drain and shift the cell's threshold voltage downward. Moreover, for a short channel device, lateral punch through by a high drain bias can cause hot hole injection and shift the threshold voltage downward.
Unintentional write: in a virtual ground array, there is always a "mirror" cell along the selected word line that is biased at the same conditions, with source and drain reversed, as the selected cell. If the cells of the array are symmetrical, the mirror cell can be unintentionally written.
The term "over-erase" refers to the condition that occurs when the threshold voltage of an electrically-erased cell becomes negative because the erase voltage is too high and/or the erase pulse width is too long.
The term "soft write" refers to the slow upward shift of a cell's threshold voltage during a read operation due to the presence of channel current. Thus, to read a cell is like writing the cell softly.
The term "intelligent erase" refers to the method by which, in order to keep the threshold voltage of an erased cell within a certain range, the erase process is controlled utilizing an internal or external controller.
The term "pre-write before erase" refers to the method by which, in order to maintain the threshold voltage of an erased cell within a certain range, all cells in the array are written to a high threshold voltage state before erasing.
Recently, Yamada et al., "A Self-convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM", IEDM, p. 307, 1991, proposed a self-convergence erasing scheme to minimize the over-erase problem associated with ETOX arrays without relying on a complicated intelligent erase scheme. With the Yamada et al. erase scheme, the cell threshold voltage distribution range after erasure can be significantly reduced. However, the reported threshold voltage range is still much wider than that of regular transistors and further verification for Megabit memory arrays remains to be done.
To eliminate the device issues associated with the ETOX cell without relying on either tight process control or critical operational sequences, Chang et al., "A Modular Flash EEPROM Technology for 0.8 .mu.m High Speed Logic Circuits", IEEE Custom Integrated Circuits Conf., p. 187, 1991, have recently proposed a source-coupling, split-gate (SCSG) flash EEPROM cell.
The FIG. 5 cross-section of the Chang et al. cell 50 shows a floating gate transistor 52 in series with an oxide-nitride-oxide (ONO) split-gate transistor 54. This cell architecture provides a tight erase voltage distribution around 1.3 volts. The source-coupling, split-gate cell 50 is written by channel hot electron injection at the drain junction through a 100 .ANG. tunnel oxide. The cell 50 is erased by tunneling at a finger 56 of the polysilicon floating gate (FG) that extends into the source diffusion, as shown in the FIG. 6 layout. In the Chang et al. cell, the word line (i.e. control gate CG) runs perpendicular to the channel region of the cell 50.
Kuo et al., "A 512-kb Flash EEPROM Embedded in a 32-b Microcontroller", IEEE J. of Solid-State Circuits, Vol. 27, p.574, 1992, have demonstrated the manufacturability of the Chang et al. array in a 512K conventional flash array with a common source bus.
Because, like the ETOX cell, the Chang et al. cell utilizes one-half contact per cell, its size is quite large and further cell scaling is limited. However, the limitations of the ETOX cell and the Chang et al. cell can be minimized by utilizing a virtual ground array architecture, that is, by replacing metal bit lines and contacts with buried diffusion bit lines in a so-called "virtual ground" architecture.
Utilizing a virtual ground architecture and the above-described ETOX cell, Woo et al., "A Poly-Buffered FACE Technology for High Density Flash Memories", Symposium on VLSI Technology, p. 73, 1991, proposed a contactless technology for realizing a very compact flash array. However, due to the symmetrical nature of the ETOX cell and the high bit line capacitance of the Mbit array, unintentional write of a neighboring unselected cell during a write operation is unavoidable.
To minimize the unintentional write problem, Yoshikawa et al., "An Asymmetrical Lightly Doped Source Cell for Virtual Ground High-Density EPROMs", IEEE Trans. on Electron Devices, Vol. 37, p. 1046, 1990, proposed an asymmetrical lightly doped source EPROM cell. However, in addition to the over-erase issue, soft write of a neighboring cell along the selected word line still limits bit line bias and cell current during read operations.
Thus, it would be highly desirable to have available an EEPROM array that eliminates the problems discussed above.